Spyridon BLIONAS

Department of Informatics and Telecommunications

University of Peloponnese

e-mail : sbli@uop.gr

 

STUDIES

1990 :       PhD, (VLSI Design for Parallel Digital Signal Processing), Technical University of Patras (Apr. 86-Jun. 90)

1986 :       MSc in Telecommunications, University of Athens

1983 :       Diploma in Physics, University of Athens

 

Professional Experience

  • Jul. 2009- today : Associated Professor in University of Peloponnese (Electronic Design of Analog and Digital Systems)
  • Feb. 2006- Jul. 2009 : Associated Professor in Technological Educational Institute of Crete (microprocessors, FPGAs)
  • Jan. 1999 – Feb. 2006 : Deputy Manager, Emerging Technologies & Markets Dept., INTRACOM S.A., responsible for research activities on design and development of VLSI-ASICs for telecommunication systems, R&D Division, of INTRACOM.
  • Oct. 1994 – Dec. 1998 : Microelectronics Section Manager Development Programmes Dept., INTRACOM S.A., responsible for Microelectronics and design and development of VLSI-ASICs for telecommunication systems.
  • Dec. 1992 -     Sept. 1994 :    Research Associate at the Institute of Microelectronics, NCSR Demokritos responsible for design of VLSI-ASICs for digital signal processing.
  • Jan. 1991 -       Nov. 1992 : Project Coordinator, Development Programmes Dept., INTRACOM S.A., responsible for the VLSI collaborative, research projects on design and development of VLSI-ASICs for telecommunication systems
  • Jul. 1989 - Jan. 1991 : Patent Examiner on “Parallel on chip architectures”, European Patent Office (EPO).
  • Jan. 1988 - Jun. 1989 : Research fellow at EC Joint Research Center (JRC) Ispra Italy, Electronics Department, on VLSI Design for Telecom Systems.
  • Jan. 1985 - Dec. 1987 : Postgraduate scholar at NCSR Demokritos on VLSI Design for Parallel Digital Signal Processing.
  • Sep. 1983 -Dec. 1987 Part time prof. (Physics-Electronics in Technical High School).

 

RESEARCH ACTIVITIES-INTERESTS

·      Analog and Digital Biomedical/Biotechnology systems development

·      Embedded systems hardware-software co-design

·      Methodologies and design of digital signal processing applications

·      Reconfigurable architectures

·      Parallel/systolic architectures

·      MEMs and Biosensors

 

RESEARCH AND DEVELOPMENT PROJECTS

1.      2012-2015, «THALES - University of Peloponnese –PROTOMI : Adaptive Technology in Optical Communications».

2.      2009-2013, Corallia Microelectronics cluster “Lab-On-Chip Microelectronic components for Lab-On-Chip Instruments for Genetic Molecular Diagnostics and Environmental Applications”.

3.      2008-2012, IST-216031, CD-Medics, “Coeliac Disease – Management, Monitoring and Diagnosis using Biosensors and an Integrated Chip  System”.

4.      2006-2009 IST-027333-ST, Micro2DNA, “Integrated polymer-based micro fluidic micro system for DNA extraction, amplification, and silicon-based detection”

5.      2002-2005, PEPER MILI-A, Wireless mile “SoC for Wireless subscribers connections in Access Network for Advanced Services, GSRT, INTRACOM S.A.

6.      2002-2004 IST-2001-34379, AMDREL “Architectures and Methodologies for Dynamic Reconfigurable Logic”.

7.      2001-2004 IST EASY “Energy aware system-on-chip design of the HIPERLAN/2 project”.

8.      2001-2004 IST ADRIATIC "Advanced Methodology for Reconfigurable SoC and Application Targeted IP-entities in wireless Communications”.

9.      2000-2002 IST SYDIC “System Design Industry Council of European Telecom Industries”.

10.  1999-2000 ESPRIT OCMP TCS_24.123 "One-Chip Low Power Transceiver for Multi-Mode Portable Phones"

11.  1997 ESPRIT LPGD ESD_LP 25.256 "Low-Power Methodology/Flow and its application to the Implementation of a DCS1800-GSM/DECT Modulator - Demodulator”

12.  1997 ESPRIT CODAC OMI_24.129 "Co-design for Applications with Embedded Cores"

13.  1996-99 ESPRIT ASPIS OMI_20.287 "Application Specific Processor and Instruction Set"

14.  1996-1998 FUSE, “First Users Action” Transfer Technology Node (ΤΤΝ), EC.

15.  1995-97 EPET II 487 "Microelectronics Industrial Projects"

16.  1993 ESPRIT 6043 QUICKCHIPS "A System Supporting ASIC Design and Providing Rapid Turnaround Prototyping".

17.  1992-94 STRIDE HELLAS 187 "Special Action VLSI-ASICs"

18.  1991-92 ESPRIT 5692 " Special Action VLSI-ASICs"

19.  1989-90 ESPRIT 802 "CAD for VLSI Systems, (CVS)", TALTEL.

 

JOURNAL PUBLICATIONS

J1.         I. Ramfos, S. Blionas and A. Birbas, “Architecture of a modular, multichannel readout system for dense electrochemical biosensor microarrays”, IOP Publishing, Measurement Science and Technology, Vol. 26, No 1, (24 November 2014)

J2.         I. Ramfos, N. Vassiliadis, S. Blionas, K. Efstathiou, A. Fragoso, C. K. O'Sullivan, “A compact hybrid-multiplexed potentiostat for real-time electrochemical biosensing applications” Elsevier, Biosensors and Bioelectronics, Vol. 47 (15 September 2013), p.p. 482–489

J3.         G. Kornaros, A. Demiris, S. Blionas : "Lab-on-Chip for Pharmacogenomics: An Embedded System Organization", Micro and Nanosystems Bentham Science Publishers, Volume 1, No1, 2009

J4.         G. Kornaros, S. Blionas : "Microarchitecture of a Lab-on-Chip Microarray for Pharmacogenomics and Molecular Diagnostics," EURASIP Journal on Advanced Signal Processing, Volume 2008, Article ID 520641, 11 pages, doi:10.1155/2008/520641.

J5.         Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, and Roberto Zafalon "Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications", Journal of Low-Power Electronics, American Scientific Publishers, vol. 2, no. 1, April 2006.

J6.         S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, “Instruction Level Energy Modeling for Pipelined Processors”, Journal of Embedded Computing 1, IOS Press, Mar. 2005, p.p.317–324.

J7.         A. Pnevmatikakis, S. Blionas and D. Triantis, “Physical Layer of Base-Band OFDM Modem - Algorithms and Performance”, J. Circuits, Systems and Computers, vol. 14, no.3, June 2005

J8.         C. Drosos, D. Metafas,  S. Blionas and G. Papadopoulos,  “Rapid prototyping of a wireless LAN implementation using a UML-based system design methodology”, IEICE Trans. on Information and Systems, Trans. on Information and Systems, Vol.E87-D, No.8, August, 2004, p.p. 2058-2069.

J9.         C. Drosos, C. Dre, D. Metafas, D. Soudris, S. Blionas, “The Low Power Analogue and Digital Baseband Processing Parts  of a Novel Dual Mode DECT/DCS1800 Terminal”, Microelectronics Journal, ELSEVIER Vol 35, No. 7, July 2004, pp 609-620.

J10.     C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, G. Papadopoulos, "Hardware-software design and validation framework for wireless LAN modems", IEE Proceedings Computers and Digital Techniques, vol. 151, no. 3, pp. 173-182, May 2004.

J11.     L. Bisdounis , C. Dre , S. Blionas , D. Metafas , A. Tatsaki , F. Ieromnimon , E. Macii , Ph. Rouzet , R. Zafalon , L. Benini,  “A Low-Power System-on-Chip (SoC) Architecture for Wireless LANs”, IEE Proceedings – Computers & Digital Techniques, Vol. 151, No. 1, January 2004, p.p. 2-15

J12.     K. Tatas, K. Siozios, D. Soudris, K. Masselos, K. Potamianos, S. Blionas and A. Thanailakis,  “Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms”, LNCS series, (Lecture Notes in Computer Science, Springer Verlag), Field Programmable Logic and Applications, vol. 2799, pp.430-439, 2003

J13.     K. Masselos1, A. Pelkonen2, M. Cupak, S. Blionas,  “Realization of Wireless Multimedia Communication Systems on Reconfigurable Platforms”, invited paper, Journal of Systems Architecture, Special Issue on Reconfigurable Systems, (Elsevier), Volume 49, Issues 4-6 , September 2003 , p.p. 155-175

J14.     C. Drosos, C. Dre,  S. Blionas, and D. Soudris, “A low power baseband processor for a portable dual mode DECT/GSM terminal”, IEICE Trans. on Information and Systems, Vol.E86-D, No.10, October, 2003, p.p. 1976-1986

J15.     S. Blionas et al., “Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip”, IEICE Trans. on Information and Systems, Vol. E86-D, No. 5 May 2003, p.p. 891-900.

J16.     G. Koutroumpezis, K. Tatas, D. Soudris, S. Blionas, K. Masselos, and A. Thanailakis,  “Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-grain Implementations LNCS series, (Lecture Notes in Computer Science, Springer Verlag), Field Programmable Logic and Applications, vol. 2438, pp.1080-1083, September 2002.

J17.     S. Blionas, et al.,  “A HIPERLAN/2-IEEE 802.11a Reconfigurable System-on-Chip”, LNCS series, (Lecture Notes in Computer Science, Springer Verlag), Field Programmable Logic and Applications, vol. 2438, pp. 1027-1036, September 2002.

J18.     H. Karathanasis, C. Dre, D. Metafas and S. V. Blionas,  "Designing a Single chip DSP for DECT and GSM/DCS-1800 Baseband Processing", Real Time Magazine, September 1996, p22-31.

J19.     H. C. Karathanasis, C. N. Dre, D. E. Metafas and S.V. Blionas, “On the Design of a Baseband Processor for DECT and GSM/DCS-1800”, Embedded Microprocessor Systems, C. Muller-Schloer et al. (Eds.), IOS Press, 1996, ISBN 90 5199 300 5 (IOS Press), ISDN 4 274 90122 X C3054 (Ohmsha).

J20.     Stavrakakis G.N., Blionas S.V., and Goutis C.E., "Dynamic Source Parameters of Corinth (central Greece) Earthquake sequence based on FFT and Iterative Maximum Entropy Techniques", Tectonophysics, Vol. 185, pp. 261-275, 1991.

J21.     Stavrakakis G.N., Blionas S.V., "Source Parameters of Some Large Earthquakes in the Eastern Mediterranean Region Based on an Iterative Maximum Entropy Technique", Pure appl. Geophys., (PAGEOPH), Vol. 132 No. 4 pp. 679-698, 1990.

                   

 

CONFERENCES PUBLICATIONS

C1.            I. Stamoulias, K. Georgoulakis, S. Blionas and G.O. Glentis, FPGA “Implementation of an MLSE Equalizer in 10Gb/s Optical Links”, 2015 IEEE International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July 2015

C2.            J. Stamoulias, S. Blionas, “Systolic Architecture of a Viterbi Equalizer for Optical Communications”, 2015 4th Workshop on Modern Circuit and Systems Technologies, University of Thessaloniki, 14-15 May 2015

C3.            Spyridon Blionas, Giorgos Papadourakis, “Implementation performance of an Embedded Architecture for Lab-on-Chip Instrumentation Control and Data Analysis”, AmiEs-2013 – 12th International Symposium on Ambient Intelligence and Embedded Systems, 19–22 September 2013, Berlin, Germany

C4.            S. Blionas, “An Embedded Architecture for Lab-on-Chip Instrumentation Control and Data Analysis”, AmiEs-2012 – 11th International Symposium on Ambient Intelligence and Embedded Systems, 20th – 22nd September 2012, Espoo, Finland.

C5.            C.-L. Sotiropoulou, L. Voudouris, C. Gentsos; S. Nikolaidis, N. Vassiliadis, A. Demiris, S. Blionas, “FPGA-based machine vision implementation for Lab-on-Chip flow detection”, Symposium on Circuits and Systems (ISCAS), 2012 IEEE International, 20-23 May 2012

C6.            S. Blionas, “Design methodology for reconfigurable implementation of the physical layer of multi standard wireless systems”, 2012 Workshop on Modern Circuit and Systems Technologies, University of Thessaloniki, 16 March 2012

C7.            S. Blionas, “Scalable low cost Architecture for Analysis of Lab-on-Chip Data”, 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, December 2010

C8.            S. Blionas, Digital and Analogue Components for a System, for Lab-on-a-Chip, WISES 2010, 8th IEEE Workshop on Intelligent Solutions in Embedded Systems, Heraklion, Crete, Greece, 8-9 July 2010

C9.            G. Kornaros, D. Meidanis, S. Chatzandroulis, Y. Papaefstathiou, and S. Blionas: “Architecture of a Consumer Lab-On-Chip for Pharmacogenomics”, IEEE Conference on Consumer Electronics, Las Vegas, published January 2008

C10.        S. Bellis, S. Blionas, J. Carrera, S. Chatzandroulis, S. Getin, K. Misiakos, A. Planat-Chretien, D. Tsoukalas, “Competitive technology approaches for Electronic Hybridisation Detection in a microsystem with microfluidics for diagnosis genetic tests”, Proceedings of 28th IEEE EMBC Annual International Conference, New York City, USA, Aug 30-Sept 3, 2006, pp. 4103-06

C11.        M. Gheorghe, S. Blionas, J. Ragoussis, and P. Galvin, “Evaluation of Silicon and Polymer substrates for fabrication of integrated microfluidic microsystems for DNA extraction and amplification”, Proceedings of 28th IEEE EMBC Annual International Conference, New York City, USA, Aug 30-Sept 3, 2006, pp. 2485-88

C12.        Panagiotis Margaronis, Spyros Blionas, Emmanouel Antonidakis, Markos Kimionis, Marios Hadjinikolaou, “Design and implementation of Automatic Gain Control (AGC) and Radio Signal Strength (RSSI), circuitry for an OFDM reconfigurable transceiver”, Proceedings of the Annual Conference on Telecommunications & Multimedia-TEMU 2005, 23-26 June 2005, Heraklion, Crete, pp. 361-368

C13.        S. Perdikouris, M. Hadjinikolaou, S. Blionas, E.Antonidakis, “Firmware design approach for an Access Point embedded system of a Hiperlan/2 WLAN”, Proceedings of the Annual Conference on Telecommunications & Multimedia-TEMU 2005, 23-26 June 2005, Heraklion, Crete, pp. 388-394

C14.        H. Zarakovitis, S. Blionas, E. Antonidakis, M. Hadjinikolaou, “Firmware design approach for a Mobile Terminal embedded system of a Hiperlan2 Wireless Local Area Network”, Proceedings of the Annual Conference on Telecommunications & Multimedia-TEMU 2005, 23-26 June 2005, Heraklion, Crete, pp. 395-403

C15.        Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, and Roberto Zafalon, “Energy-Aware System-on-Chip for 5 GHz Wireless LANs”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, Sep. 2005

C16.        C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, “A Multi-level Hardware-Software Validation Methodology for Wireless Network Applications “,Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, Sep. 2004.

C17.        K. Masselos, S. Blionas, J-Y. Mignolet, A. Foster, D. Soudris, S. Nikolaidis, “Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, Sep. 2004.

C18.        Masselos, D. Soudris, S. Blionas, “A Reconfigurable System-on-Chip Platform for Wireless Communications”, IEEE Int. Workshop on Wireless Circuits and Systems Vancouver, Canada, May 2004

C19.        E. Theochari 1 , K. Tatas D. J. Soudris, Masselos, K. Potamianos, S. Blionas and A. Thanailakis, “A reusable ip fft core for dsp applications”, IEEE International Symposium on Circuits and Systems 2004 (IEEE ISCAS 2004), Vancouver, Canada, May 2004

C20.        S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, “Instruction Level Energy Modeling for Pipelined Processors”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sep. 2003.

C21.        D. Soudris, M. Kesoulis, C. Koukourlis, S. Blionas, “Alternative direct digital frequency synthesizer architectures with reduced memory size”, IEEE International Symposium on Circuits and Systems 2003 (IEEE ISCAS 2003), Bangkok,Thailand, May 2003

C22.        K. Masselos, S. Blionas, “Reconfigurability requirements of wireless communication systems” IEEE Workshop on Heterogeneous reconfigurable Systems on Chip (SoC), Chances, Applications, Trends, April 2002, Hamburg, Germany

C23.        D. Soudris, K. Masselos, S. Blionas, S. Siskos, S. Nikolaidis and K. Tatas, “AMDREL: On Designing an Embedded FPGA Structure for the Future Reconfigurable SoC for Wireless Communication Applications”, IEEE Workshop on Heterogeneous reconfigurable Systems on Chip (SoC), Chances, Applications, Trends, April 2002, Hamburg, Germany

C24.        S. Blionas, K. Masselos, C. Dre, F. Ieromnimon, T. Pagonis, A. Pneymatikakis, A. Tatsaki, T.Trimis, A. Vontzalidis and D. Metafas, “Design Story : A Hiperlan2/IEEE802.11x Reconfigurable SoC for indoor WLANs and outdoor wireless links. A pilot project for the future generation configurable wireless communications products” IEEE Workshop on Heterogeneous reconfigurable Systems on Chip (SoC), Chances, Applications, Trends, April 2002, Hamburg, Germany

C25.        C. Drosos, C. Dre, D. Metafas, D. Soudris, S. Blionas, “The low power baseband processing parts of a novel dual mode DECT/GSM terminal”, International IEEE Conference on Electronics, Circuits, and Systems (ICECS), 2-6 Sept. 2001, Malta.

C26.        C.Drosos, C. Dre,  S. Blionas, D. Soudris “On the implementation of a baseband processor for a portable Dual Mode DECT/GSM terminal” , IEEE International Symposium on Circuits and Systems, (ISCAS), May 6 - 9, 2001 Sydney, Australia ISCAS'2001, Sydney.

C27.        Drosos, C. Dre, K. Potamianos and S. Blionas, "A MCM-L Board for the Basaband Processor of a Dual Mode Wireless Terminal", MMN 2000 (First Conference on Microelectronics, Microsystems and Nanotechnology), 20-22 November 2000.

C28.        F. Ieromnimon, C. Dre, D. Metafas, C. Drosos, V. Koratzinos, A. Alexopoulou, S. Blionas, “On the Integration of Diverse Testing Strategies in a Low-Power Processor”, Design Automation & Test in Europe Conference (DATE2000), Paris, France, March 2000.

C29.        H. Karathanasis, C. Dre, D. Metafas and S. Blionas "On Designing a DSP for DECT and GSM/DCS1800 Baseband Processor", EMSYS 96 OMI sixth Annual Conference, Berlin, September 1996.

C30.        D. Metafas, H. Karathanasis, and S. Blionas "Industrial Approach in Designing Methodologies for Mobile Communications Systems", Seventh IEEE International Workshop on Rapid System Prototyping, Thessaloniki, Greece, June 1996.

C31.        S. Blionas, I. Bogdos, A. Bonomo, M. Italiano, L. Lavagno, M. L. Maggiulli, M. Mesturino, M. Paolini, I. Stamelos, "ASIC Design with the BACH Behavioural Synthesis System" The European Design Automation Conference Glasgow, Scotland Poster Session 2, March 1990.

C32.        S. Blionas, A. Balboni, G. Gorla, "A  VLSI Linear Array of  Processors for the Viterbi Algorithm  Designed  with an Approach Independent from Design Language and from Implementation Technology" Proc. Int'l Conf. on VLSI and CAD pp. 67-70 Octob. 1989.

C33.        S. Blionas A. Balboni, G. Gorla, S. Barbagalo, A. Burri, R. Castellan, S. Ravaglia, "A Special Purpose Technology Independent SIMD Parallel Processor for the Viterbi Algorithm", Proc. of IFIP Workshop on Parallel Architectures on Silicon: from Systolic Arrays to Neural Networks ", Grenoble France pp. 227-239, December 1989.

C34.        C.E. Goutis and S.V. Blionas, "Array processor for solving noisy Toeplitz systems", in Proceedings of conference in Integrated Circuit Technology I, Limerick, Ireland, pp. 65-72, 1986.

                                                                                  

NATIONAL CONFERENCES

Ε1. C. Drosos, C. Dre, D. Soudris, G. Kalivas and S. Blionas “On the Design of a Low Power Modulator/Demodulator for DECT/GSM”, in Proc. of 1st Conf. Microelectronics, Microsystems, & Nanotechnology, November 20-22, 2000, Athens, pp. 309-312.

 

PATENT APPLICATIONS                                                                      

  1. Greek Patent Application : S. Blionas, A. Demiris, GR20130100091, 31 January 2013 (“Integrated System for electronic detection of biological components with  Visual Control, based on Microfluidics (Lab-on-Chip)”)
  2. Greek Patent Application : I. Ramfos, S. Blionas, GR20120100269, 22 May 2012, (“Parameterisable, autocallibrated circuit for parallel measurements of electrochemical sensors under continuous bias”)
  3. Greek Patent Application : A. Demiris, S. Blionas,  GR20110100390/2011-02211, 5 July 2011 (“Integrated System for the Visual Control, Quantitative and Qualitative Flow Measurement in Microfluidics”)
  4. European Patent Application : S. Blionas, “Viterbi Equaliser for Maximum Likelihood Estimation”, EP0671836A2, European Patent Office, 1995.
  5. Greek Patent Application : S. Blionas, “Viterbi Equaliser for Maximum Likelihood Estimation”, GR 94010109, O.B.I. 1994.

ΣΠΥΡΙΔΩΝ ΜΠΛΙΩΝΑΣ

Τμήμα Πληροφορικής & Τηλεπικοινωνιών

Πανεπιστήμιο Πελοποννήσου

τηλ.: 2710 372239

e-mail : sbli@uop.gr

 

ΣΠΟΥΔΕΣ

 

  • Διδακτορικό Δίπλωμα από το Τμήμα Ηλεκτρολόγων Μηχ. του Πανεπιστημίου Πατρών, Εργ. Σχεδιασμού Ολοκληρωμένων Κυκλωμάτων. Τίτλος Διατριβής: “Σχεδιασμός κυκλωμάτων υπερυψηλής πυκνότητας  για Παράλληλη Επεξεργασία Ψηφιακού Σήματος” (1990)
  • Μεταπτυχιακό δίπλωμα Τηλεπικοινωνιών (Ραδιοηλεκτρολόγος), Πανεπιστήμιο Αθηνών (1986)

§         Πτυχίο Φυσικής, Πανεπιστήμιο Αθηνών (1983)

 

ΕΠΑΓΓΕΛΜΑΤΙΚΗ ΕΜΠΕΙΡΙΑ

  • Ιούλ.. 2009- : Αναπληρωτής Καθηγητής με γνωστικό αντικείμενο «Ηλεκτρονική σχεδίαση αναλογικών και ψηφιακών συστημάτων» στο Πανεπιστήμιο Πελοποννήσου, Τμήμα Πληροφορικής & Τηλεπικοινωνιών.
  • Φεβ. 2006- Ιούλ. 2009 : Αναπληρωτής Καθηγητής με γνωστικό αντικείμενο «Μικροϋπολογιστές», στα ΤΕΙ Κρήτης, Τμήμα Εφαρμοσμένης Πληροφορικής και Πολυμέσων της Σχολής Τεχνολογικών Εφαρμογών
  • Ιαν. 1999 – Φεβ. 2006 : Αναπληρωτής Διευθυντής Αναπτυξιακών Προγραμμάτων, Υπεύθυνος ερευνητικών δραστηριοτήτων σχεδιασμού και υλοποίησης τηλεπικοινωνιακών συστημάτων με χρήση Ολοκληρωμένων Κυκλωμάτων Eιδικού Σκοπού (VLSI-ASICs), στην Γενική Διεύθυνση Έρευνας & Ανάπτυξης της εταιρείας ΙΝΤΡΑΚΟΜ Α.Ε.
  • Οκτ. 1994 – Δεκ. 1998 : Υπεύθυνος ερευνητικών δραστηριοτήτων Μικροηλεκτρονικής και σχεδιασμού Ολοκληρωμένων Κυκλωμάτων Eιδικού Σκοπού (VLSI-ASICs) για Τηλεπικοινωνιακά συστήματα, στην Διεύθυνση Αναπτυξιακών Προγραμμάτων της εταιρείας ΙΝΤΡΑΚΟΜ Α.Ε.
  • Δεκ. 1992 -  Σεπτ. 1994 : Ερευνητής στο Ινστιτούτο Μικροηλεκτρονικής του ΕΚΕΦΕ ΔΗΜΟΚΡΙΤΟΣ σε θέματα σχεδιασμού VLSI κυκλωμάτων για επεξεργασία ψηφιακού σήματος.
  • Ιαν. 1991 - Νοέμ. 1992 :Υπεύθυνος συντονισμού προγραμμάτων σε σχεδιασμό VLSI κυκλωμάτων ειδικού σκοπού (ASICs), για Τηλεπικοινωνιακά συστήματα, στην Διεύθυνση Αναπτυξιακών Προγραμμάτων της εταιρείας ΙΝΤΡΑΚΟΜ Α.Ε.
  • Ιουλ. 1989 - Ιαν. 1991            : Κριτής Ευρεσιτεχνιών σε θέματα "Αρχιτεκτονικών Παράλληλων Υπολογιστών σε chip" για το Ευρωπαϊκό Γραφείο Ευρεσιτεχνιών.
  • Ιαν. 1988 - Ιουν. 1989 :Υπότροφος ερευνητής στο "Κοινό ερευνητικό κέντρο (JRC) της Επιτροπής των Ευρωπαϊκών Κοινοτήτων  στο Ισπρα της Ιταλίας τμήμα Ηλεκτρονικής, σε σχεδιασμό VLSI κυκλωμάτων, για Τηλεπικοινωνιακά συστήματα.
  • Ιαν. 1985 - Δεκ. 1987 : Μεταπτυχιακός υπότροφος στο Ερευνητικό Κέντρο ΔΗΜΟΚΡΙΤΟΣ σε σχεδιασμό κυκλωμάτων VLSI για παράλληλη επεξεργασία ψηφιακών σημάτων.
  • Σεπ. 1983 - Δεκ. 1987 Ωρομίσθιος Καθηγητής Μέσης Εκπαίδευσης (Φυσικός-Ηλεκτρονικός) σε Τεχνικό Λύκειο.

 

ΕΡΕΥΝΗΤΙΚΕΣ ΔΡΑΣΤΗΡΙΟΤΗΤΕΣ-ΕΝΔΙΑΦΕΡΟΝΤΑ

·      Ανάπτυξη εφαρμογών και ψηφιακών/αναλογικών συστημάτων στον χώρο της Βιοτεχνολογίας

·      Σχεδιασμός Υλικού και Λογισμικού Ενσωματωμένων Συστημάτων

·      Μεθοδολογίες και Σχεδιασμός Εφαρμογών Ψηφιακής Επεξεργασίας Σήματος

·      Επαναπροσδιοριζόμενες Αρχιτεκτονικές

·      Παράλληλες/Συστολικές Αρχιτεκτονικές

·      MEMs and Biosensors

 

ΔΙΔΑΚΤΙΚΟ ΕΡΓΟ

  • Πανεπιστήμιο Πελοποννήσου, Τμήμα Πληροφορικής & Τηλεπικοινωνιών, τα ακόλουθα προπτυχιακά μαθήματα:
    • «Ηλεκτρονική»,  Υποχρεωτικό μάθημα, 2ου έτους, 2008-2009, 2009-2010, 2010-2011, 2011-2012,2012-2013, 2013-2014
    • «Γραμμικά Ηλεκτρικά κυκλώματα», Υποχρεωτικό μάθημα, 1ου έτους, 2009-2010, 2010-2011, 2011-2012,2012-2013
    • «Λογική Σχεδίαση», Υποχρεωτικό μάθημα, 1ου έτους, 2011, 2011-2012,2012-2013
    • Ψηφιακή σχεδίαση συστημάτων» , μάθημα επιλογής κατεύθυνσης 3ου έτους, 20013-2014
    • «Ηλεκτρονικά Τηλεπικοινωνιακά Συστήματα», Ελεύθερο μάθημα 3ου έτους, 2010-2011, 2011-2012,
  • Πανεπιστήμιο Πελοποννήου, Πρόγραμμα Μεταπτυχιακών Σπουδών (Π.Μ.Σ.) στην Επιστήμη και την Τεχνολογία Υπολογιστών, «Ασύρματα δίκτυα αισθητήρων», 2013-2014
  • ΤΕΙ Κρήτης, Τμήμα Εφαρμοσμένης Πληροφορικής και Πολυμέσων της Σχολής Τεχνολογικών Εφαρμογών τα ακόλουθα προπτυχιακά μαθήματα:
    • “Μικρουπολογιστές”, μάθημα επιλογής υποχρεωτικό 3ου έτους, 2006-2007, 2007-2008, 2008-2009
    • ”Υλοποίηση Ψηφιακών Συστημάτων Ασύρματης Επικοινωνίας σε VLSI”, μάθημα επιλογής υποχρεωτικό 3ου έτους, 2006-2007, 2007-2008, 2008-2009
    •  «Ενσωματωμένα συστήματα» μάθημα επιλογής υποχρεωτικό 3ου έτους, 2006-2007, 2007-2008, 2008-2009
  • Α.Σ.Ε.Τ.Ε.Μ.-ΣΕΛΕΤΕ Τμήμα Ηλεκτρονικής, “Μικροϋπολογιστές”, Υποχρεωτικό μάθημα, 3ου έτους 1999-2000

 

Επίβλεψη Μεταπτυχιακών διπλωματικών εργασιών

  • Brunell University, 1 φοιτητής 2001-2002, 2 φοιτητές 2002-2003
  • Πανεπιστήμιο Πελοποννήσου, Πρόγραμμα Μεταπτυχιακών Σπουδών (Π.Μ.Σ.) στην Επιστήμη και την Τεχνολογία Τηλεπικοινωνιών, 1 φοιτητής 2011-2012

 

ΣυμμετοχΗ σε ΕΡΕΥΝΗΤΙΚΑ ΚΑΙ ΑΝΑΠΤΥΞΙΑΚΑ πρΟγρΑΜΜΑΤΑ

Ως Επιστημονικός Υπεύθυνος:

1.    2006-2009  IST-027333-ST, Micro2DNA, “Integrated polymer-based micro fluidic micro system for DNA extraction, amplification, and silicon-based detection” σαν υπεύθυνος όλου του έργου και επικεφαλής της σχεδίασης του Point of Care αναλογικού-ψηφιακού συστήματος για το μικροσύστημα..

2.    1999-2000 ESPRIT OCMP TCS_24.123 "One-Chip Low Power Transceiver for Multi-Mode Portable Phones" σαν τεχνικός υπεύθυνος ολοκλήρωσης και ελέγχου του αναλογικού και ψηφιακού συστήματος.

3.    1996-99 ESPRIT ASPIS OMI_20.287 "Application Specific Processor and Instruction Set" σαν υπεύθυνος όλου του έργου και σχεδιαστής του Viterbi Equalizer του chip.

4.    1997 ESPRIT LPGD ESD_LP 25.256 "Low-Power Methodology/Flow and its application to the Implementation of a DCS1800-GSM/DECT Modulator - Demodulator” σαν τεχνικός υπεύθυνος της ολοκλήρωσης του διαμορφωτή/αποδιαμορφωτή με το υπόλοιπο chip (αναλογικό και ψηφιακό τμήμα).

5.    1997 ESPRIT CODAC OMI_24.129 "Co-design for Applications with Embedded Cores" σαν project co-ordinator και τεχνικός υπεύθυνος της INTRAΚOM στο τμήμα που αφορούσε το hardware.

6.    1995-97 ΕΠΕΤ II 487 "ΒΙΟΜΗΧΑΝΙΚΑ ΠΡΟΪΟΝΤΑ ΜΙΚΡΟΗΛΕΚΤΡΟΝΙΚΗΣ" σαν υπεύθυνος συνολικά του έργου και μηχανικός ολοκλήρωσης του συστήματος της ΙΝΤΡΑΚΟΜ.

7.    1992-94 STRIDE HELLAS 187 "Σχεδιασμός και προτοτυποποίηση VLSI κυκλωμάτων ειδικού σκοπού (VLSI-ASICs)" σαν τεχνικός υπεύθυνος του έργου και σχεδιαστής της εφαρμογής ASIC της ΙΝΤΡΑΚΟΜ για σύστημα ισοστάθμισης δεδομένων.

8.    1991-92 ESPRIT 5692 "Σχεδιασμός VLSI κυκλωμάτων ειδικού σκοπού (VLSI-ASICs)", σαν τεχνικός υπεύθυνος του έργου και σχεδιαστής της εφαρμογής PCM της ΙΝΤΡΑΚΟΜ.

 

Ως Ερευνητής

1.    2012-2015, «ΘΑΛΗΣ- Πανεπιστήμιο Πελοποννήσου –ΠΡΟΤΟΜΗ: ΠΡΟσαρμοστική Τεχνολογία στην Οπτική Μετάδοση», Συμμετοχή στον σχεδιασμό του συστήματος επεξεργασίας σήματος και της υλοποίησης σε FPGA.

2.    2009-2013, Corallia Microelectronics cluster “Lab-On-Chip Στοιχεία Μικροηλεκτρονικής για Lab-On-Chip Όργανα Μοριακών Αναλύσεων για Γενετικές και Περιβαλλοντικές Εφαρμογές”, με κύρια συμμετοχή στην ολοκλήρωση του αναλογικο-ψηφιακού συστήματος του Point of Care, 1/10/2009-31/12/2012.

3.    2008-2012, IST-216031, CD-Medics, “Coeliac Disease – Management, Monitoring and Diagnosis using Biosensors and an Integrated Chip  System”, με κύρια συμμετοχή στο WP5 “Communications” (υπεύθυνος), και σημαντική συμμετοχή στο WP6 “Instrumentation” για την ανάπτυξη του ψηφιακού και αναλογικού συστήματος του Point of Care, 1/02/2008-31/12/2012.

4.    2002-2005, ΠΕΠΕΡ ΜΙΛΙ-Α, Ασύρματο μίλι “Ασύρματες συνδρομητικές συνδέσεις δικτύου πρόσβασης προηγμένων υπηρεσιών υλοποιημένες με συστήματα σε πυρίτιο”, με χρηματοδότηση από την ΓΓΕΤ, INTRACOM S.A., κύρια συμμετοχη στην ολοκλήρωση του συστήματος.

5.    2002-2004 IST-2001-34379, AMDREL “Architectures and Methodologies for Dynamic Reconfigurable Logic” σαν μέλος της ερευνητικής ομάδας και υπεύθυνος του συστήματος επίδειξης.

6.    2001-2004 IST EASY “Energy aware system-on-chip design of the HIPERLAN/2 project” σαν μέλος της ερευνητικής ομάδας και υπεύθυνος του συστήματος επίδειξης.

7.    2001-2004 IST ADRIATIC "Advanced Methodology for Reconfigurable SoC and Application Targeted IP-entities in wireless Communications” σαν μέλος της ερευνητικής ομάδας και υπεύθυνος του συστήματος επίδειξης.

8.    2000-2002 IST SYDIC “System Design Industry Council of European Telecom Industries” σαν μέλος της ομάδας καθορισμού προδιαγραφών.

9.    1996-1998 FUSE, “First Users Action” στα πλαίσια του Transfer Technology Node (ΤΤΝ) με χρηματοδότηση από την Ευρωπαϊκή Ένωση,

10.1993 ESPRIT 6043 QUICKCHIPS "A System Supporting ASIC Design and Providing Rapid Turnaround Prototyping", σαν σχεδιαστής στην ανάπτυξη τμήματος του έργου (Uncommitted Flow, Demonstrator Circuits) και προετοιμασία των workpackages όλου του έργου.

11.1989-90 ESPRIT 802 "CAD for VLSI Systems, (CVS)" σαν σχεδιαστής VLSI κυκλώματος (ASIC), για έλεγχο συστήματος GSM της ITALTEL.

 

Εργασίες Δημοσιευμένες σε έγκυρα Διεθνή Περιοδικά με Κριτές

J22.     I. Ramfos, S. Blionas and A. Birbas, “Architecture of a modular, multichannel readout system for dense electrochemical biosensor microarrays”, IOP Publishing, Measurement Science and Technology, Vol. 26, No 1, (24 November 2014)

J23.     I. Ramfos, N. Vassiliadis, S. Blionas, K. Efstathiou, A. Fragoso, C. K. O'Sullivan, “A compact hybrid-multiplexed potentiostat for real-time electrochemical biosensing applications” Elsevier, Biosensors and Bioelectronics, Vol. 47 (15 September 2013), p.p. 482–489

J24.     G. Kornaros, A. Demiris, S. Blionas : "Lab-on-Chip for Pharmacogenomics: An Embedded System Organization", Micro and Nanosystems Bentham Science Publishers, Volume 1, No1, 2009

J25.     G. Kornaros, S. Blionas : "Microarchitecture of a Lab-on-Chip Microarray for Pharmacogenomics and Molecular Diagnostics," EURASIP Journal on Advanced Signal Processing, Volume 2008, Article ID 520641, 11 pages, doi:10.1155/2008/520641.

J26.     Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, and Roberto Zafalon "Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications", Journal of Low-Power Electronics, American Scientific Publishers, vol. 2, no. 1, April 2006.

J27.     S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, “Instruction Level Energy Modeling for Pipelined Processors”, Journal of Embedded Computing 1, IOS Press, Mar. 2005, p.p.317–324.

J28.     A. Pnevmatikakis, S. Blionas and D. Triantis, “Physical Layer of Base-Band OFDM Modem - Algorithms and Performance”, J. Circuits, Systems and Computers, vol. 14, no.3, June 2005

J29.     C. Drosos, D. Metafas,  S. Blionas and G. Papadopoulos,  “Rapid prototyping of a wireless LAN implementation using a UML-based system design methodology”, IEICE Trans. on Information and Systems, Trans. on Information and Systems, Vol.E87-D, No.8, August, 2004, p.p. 2058-2069.

J30.     C. Drosos, C. Dre, D. Metafas, D. Soudris, S. Blionas, “The Low Power Analogue and Digital Baseband Processing Parts  of a Novel Dual Mode DECT/DCS1800 Terminal”, Microelectronics Journal, ELSEVIER Vol 35, No. 7, July 2004, pp 609-620.

J31.     C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, G. Papadopoulos, "Hardware-software design and validation framework for wireless LAN modems", IEE Proceedings Computers and Digital Techniques, vol. 151, no. 3, pp. 173-182, May 2004.

J32.     L. Bisdounis , C. Dre , S. Blionas , D. Metafas , A. Tatsaki , F. Ieromnimon , E. Macii , Ph. Rouzet , R. Zafalon , L. Benini,  “A Low-Power System-on-Chip (SoC) Architecture for Wireless LANs”, IEE Proceedings – Computers & Digital Techniques, Vol. 151, No. 1, January 2004, p.p. 2-15

J33.     K. Tatas, K. Siozios, D. Soudris, K. Masselos, K. Potamianos, S. Blionas and A. Thanailakis,  “Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms”, LNCS series, (Lecture Notes in Computer Science, Springer Verlag), Field Programmable Logic and Applications, vol. 2799, pp.430-439, 2003

J34.     K. Masselos1, A. Pelkonen2, M. Cupak, S. Blionas,  “Realization of Wireless Multimedia Communication Systems on Reconfigurable Platforms”, invited paper, Journal of Systems Architecture, Special Issue on Reconfigurable Systems, (Elsevier), Volume 49, Issues 4-6 , September 2003 , p.p. 155-175

J35.     C. Drosos, C. Dre,  S. Blionas, and D. Soudris, “A low power baseband processor for a portable dual mode DECT/GSM terminal”, IEICE Trans. on Information and Systems, Vol.E86-D, No.10, October, 2003, p.p. 1976-1986

J36.     S. Blionas et al., “Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip”, IEICE Trans. on Information and Systems, Vol. E86-D, No. 5 May 2003, p.p. 891-900.

J37.     G. Koutroumpezis, K. Tatas, D. Soudris, S. Blionas, K. Masselos, and A. Thanailakis,  “Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-grain Implementations LNCS series, (Lecture Notes in Computer Science, Springer Verlag), Field Programmable Logic and Applications, vol. 2438, pp.1080-1083, September 2002.

J38.     S. Blionas, et al.,  “A HIPERLAN/2-IEEE 802.11a Reconfigurable System-on-Chip”, LNCS series, (Lecture Notes in Computer Science, Springer Verlag), Field Programmable Logic and Applications, vol. 2438, pp. 1027-1036, September 2002.

J39.     H. Karathanasis, C. Dre, D. Metafas and S. V. Blionas,  "Designing a Single chip DSP for DECT and GSM/DCS-1800 Baseband Processing", Real Time Magazine, September 1996, p22-31.

J40.     H. C. Karathanasis, C. N. Dre, D. E. Metafas and S.V. Blionas, “On the Design of a Baseband Processor for DECT and GSM/DCS-1800”, Embedded Microprocessor Systems, C. Muller-Schloer et al. (Eds.), IOS Press, 1996, ISBN 90 5199 300 5 (IOS Press), ISDN 4 274 90122 X C3054 (Ohmsha).

J41.     Stavrakakis G.N., Blionas S.V., and Goutis C.E., "Dynamic Source Parameters of Corinth (central Greece) Earthquake sequence based on FFT and Iterative Maximum Entropy Techniques", Tectonophysics, Vol. 185, pp. 261-275, 1991.

J42.     Stavrakakis G.N., Blionas S.V., "Source Parameters of Some Large Earthquakes in the Eastern Mediterranean Region Based on an Iterative Maximum Entropy Technique", Pure appl. Geophys., (PAGEOPH), Vol. 132 No. 4 pp. 679-698, 1990.

 

Εργασίες Δημοσιευμένες σε Πρακτικά Διεθνών Συνεδρίων με Κριτές

C35.        I. Stamoulias, K. Georgoulakis, S. Blionas and G.O. Glentis, FPGA “Implementation of an MLSE Equalizer in 10Gb/s Optical Links”, 2015 IEEE International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July 2015

C36.        J. Stamoulias, S. Blionas, “Systolic Architecture of a Viterbi Equalizer for Optical Communications”, 2015 4th Workshop on Modern Circuit and Systems Technologies, University of Thessaloniki, 14-15 May 2015

C37.        Spyridon Blionas, Giorgos Papadourakis, “Implementation performance of an Embedded Architecture for Lab-on-Chip Instrumentation Control and Data Analysis”, AmiEs-2013 – 12th International Symposium on Ambient Intelligence and Embedded Systems, 19–22 September 2013, Berlin, Germany

C38.        S. Blionas, “An Embedded Architecture for Lab-on-Chip Instrumentation Control and Data Analysis”, AmiEs-2012 – 11th International Symposium on Ambient Intelligence and Embedded Systems, 20th – 22nd September 2012, Espoo, Finland.

C39.        C.-L. Sotiropoulou, L. Voudouris, C. Gentsos; S. Nikolaidis, N. Vassiliadis, A. Demiris, S. Blionas, “FPGA-based machine vision implementation for Lab-on-Chip flow detection”, Symposium on Circuits and Systems (ISCAS), 2012 IEEE International, 20-23 May 2012

C40.        S. Blionas, “Design methodology for reconfigurable implementation of the physical layer of multi standard wireless systems”, 2012 Workshop on Modern Circuit and Systems Technologies, University of Thessaloniki, 16 March 2012

C41.        S. Blionas, “Scalable low cost Architecture for Analysis of Lab-on-Chip Data”, 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, December 2010

C42.        S. Blionas, Digital and Analogue Components for a System, for Lab-on-a-Chip, WISES 2010, 8th IEEE Workshop on Intelligent Solutions in Embedded Systems, Heraklion, Crete, Greece, 8-9 July 2010

C43.        G. Kornaros, D. Meidanis, S. Chatzandroulis, Y. Papaefstathiou, and S. Blionas: “Architecture of a Consumer Lab-On-Chip for Pharmacogenomics”, IEEE Conference on Consumer Electronics, Las Vegas, published January 2008

C44.        S. Bellis, S. Blionas, J. Carrera, S. Chatzandroulis, S. Getin, K. Misiakos, A. Planat-Chretien, D. Tsoukalas, “Competitive technology approaches for Electronic Hybridisation Detection in a microsystem with microfluidics for diagnosis genetic tests”, Proceedings of 28th IEEE EMBC Annual International Conference, New York City, USA, Aug 30-Sept 3, 2006, pp. 4103-06

C45.        M. Gheorghe, S. Blionas, J. Ragoussis, and P. Galvin, “Evaluation of Silicon and Polymer substrates for fabrication of integrated microfluidic microsystems for DNA extraction and amplification”, Proceedings of 28th IEEE EMBC Annual International Conference, New York City, USA, Aug 30-Sept 3, 2006, pp. 2485-88

C46.        Panagiotis Margaronis, Spyros Blionas, Emmanouel Antonidakis, Markos Kimionis, Marios Hadjinikolaou, “Design and implementation of Automatic Gain Control (AGC) and Radio Signal Strength (RSSI), circuitry for an OFDM reconfigurable transceiver”, Proceedings of the Annual Conference on Telecommunications & Multimedia-TEMU 2005, 23-26 June 2005, Heraklion, Crete, pp. 361-368

C47.        S. Perdikouris, M. Hadjinikolaou, S. Blionas, E.Antonidakis, “Firmware design approach for an Access Point embedded system of a Hiperlan/2 WLAN”, Proceedings of the Annual Conference on Telecommunications & Multimedia-TEMU 2005, 23-26 June 2005, Heraklion, Crete, pp. 388-394

C48.        H. Zarakovitis, S. Blionas, E. Antonidakis, M. Hadjinikolaou, “Firmware design approach for a Mobile Terminal embedded system of a Hiperlan2 Wireless Local Area Network”, Proceedings of the Annual Conference on Telecommunications & Multimedia-TEMU 2005, 23-26 June 2005, Heraklion, Crete, pp. 395-403

C49.        Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, and Roberto Zafalon, “Energy-Aware System-on-Chip for 5 GHz Wireless LANs”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, Sep. 2005

C50.        C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, “A Multi-level Hardware-Software Validation Methodology for Wireless Network Applications “,Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, Sep. 2004.

C51.        K. Masselos, S. Blionas, J-Y. Mignolet, A. Foster, D. Soudris, S. Nikolaidis, “Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, Sep. 2004.

C52.        Masselos, D. Soudris, S. Blionas, “A Reconfigurable System-on-Chip Platform for Wireless Communications”, IEEE Int. Workshop on Wireless Circuits and Systems Vancouver, Canada, May 2004

C53.        E. Theochari 1 , K. Tatas D. J. Soudris, Masselos, K. Potamianos, S. Blionas and A. Thanailakis, “A reusable ip fft core for dsp applications”, IEEE International Symposium on Circuits and Systems 2004 (IEEE ISCAS 2004), Vancouver, Canada, May 2004

C54.        S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, “Instruction Level Energy Modeling for Pipelined Processors”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sep. 2003.

C55.        D. Soudris, M. Kesoulis, C. Koukourlis, S. Blionas, “Alternative direct digital frequency synthesizer architectures with reduced memory size”, IEEE International Symposium on Circuits and Systems 2003 (IEEE ISCAS 2003), Bangkok,Thailand, May 2003

C56.        K. Masselos, S. Blionas, “Reconfigurability requirements of wireless communication systems” IEEE Workshop on Heterogeneous reconfigurable Systems on Chip (SoC), Chances, Applications, Trends, April 2002, Hamburg, Germany

C57.        D. Soudris, K. Masselos, S. Blionas, S. Siskos, S. Nikolaidis and K. Tatas, “AMDREL: On Designing an Embedded FPGA Structure for the Future Reconfigurable SoC for Wireless Communication Applications”, IEEE Workshop on Heterogeneous reconfigurable Systems on Chip (SoC), Chances, Applications, Trends, April 2002, Hamburg, Germany

C58.        S. Blionas, K. Masselos, C. Dre, F. Ieromnimon, T. Pagonis, A. Pneymatikakis, A. Tatsaki, T.Trimis, A. Vontzalidis and D. Metafas, “Design Story : A Hiperlan2/IEEE802.11x Reconfigurable SoC for indoor WLANs and outdoor wireless links. A pilot project for the future generation configurable wireless communications products” IEEE Workshop on Heterogeneous reconfigurable Systems on Chip (SoC), Chances, Applications, Trends, April 2002, Hamburg, Germany

C59.        C. Drosos, C. Dre, D. Metafas, D. Soudris, S. Blionas, “The low power baseband processing parts of a novel dual mode DECT/GSM terminal”, International IEEE Conference on Electronics, Circuits, and Systems (ICECS), 2-6 Sept. 2001, Malta.

C60.        C.Drosos, C. Dre,  S. Blionas, D. Soudris “On the implementation of a baseband processor for a portable Dual Mode DECT/GSM terminal” , IEEE International Symposium on Circuits and Systems, (ISCAS), May 6 - 9, 2001 Sydney, Australia ISCAS'2001, Sydney.

C61.        Drosos, C. Dre, K. Potamianos and S. Blionas, "A MCM-L Board for the Basaband Processor of a Dual Mode Wireless Terminal", MMN 2000 (First Conference on Microelectronics, Microsystems and Nanotechnology), 20-22 November 2000.

C62.        F. Ieromnimon, C. Dre, D. Metafas, C. Drosos, V. Koratzinos, A. Alexopoulou, S. Blionas, “On the Integration of Diverse Testing Strategies in a Low-Power Processor”, Design Automation & Test in Europe Conference (DATE2000), Paris, France, March 2000.

C63.        H. Karathanasis, C. Dre, D. Metafas and S. Blionas "On Designing a DSP for DECT and GSM/DCS1800 Baseband Processor", EMSYS 96 OMI sixth Annual Conference, Berlin, September 1996.

C64.        D. Metafas, H. Karathanasis, and S. Blionas "Industrial Approach in Designing Methodologies for Mobile Communications Systems", Seventh IEEE International Workshop on Rapid System Prototyping, Thessaloniki, Greece, June 1996.

C65.        S. Blionas, I. Bogdos, A. Bonomo, M. Italiano, L. Lavagno, M. L. Maggiulli, M. Mesturino, M. Paolini, I. Stamelos, "ASIC Design with the BACH Behavioural Synthesis System" The European Design Automation Conference Glasgow, Scotland Poster Session 2, March 1990.

C66.        S. Blionas, A. Balboni, G. Gorla, "A  VLSI Linear Array of  Processors for the Viterbi Algorithm  Designed  with an Approach Independent from Design Language and from Implementation Technology" Proc. Int'l Conf. on VLSI and CAD pp. 67-70 Octob. 1989.

C67.        S. Blionas A. Balboni, G. Gorla, S. Barbagalo, A. Burri, R. Castellan, S. Ravaglia, "A Special Purpose Technology Independent SIMD Parallel Processor for the Viterbi Algorithm", Proc. of IFIP Workshop on Parallel Architectures on Silicon: from Systolic Arrays to Neural Networks ", Grenoble France pp. 227-239, December 1989.

C68.        C.E. Goutis and S.V. Blionas, "Array processor for solving noisy Toeplitz systems", in Proceedings of conference in Integrated Circuit Technology I, Limerick, Ireland, pp. 65-72, 1986.

 

Εργασίες Δημοσιευμένες σε Πρακτικά Εθνικών Συνεδρίων με Κριτές

Ε2. C. Drosos, C. Dre, D. Soudris, G. Kalivas and S. Blionas “On the Design of a Low Power Modulator/Demodulator for DECT/GSM”, in Proc. of 1st Conf. Microelectronics, Microsystems, & Nanotechnology, November 20-22, 2000, Athens, pp. 309-312.

 

Αιτήσεις για Διπλώματα Ευρεσιτεχνίας                                                   

  1. Ελληνική αίτηση διπλώματος ευρεσιτεχνίας : Σ. Μπλιώνας, Α. Δεμίρης“, “Ολοκληρωμένο σύστημα ανίχνευσης βιολογικών συστατικών, με οπτικό έλεγχο και χρήση Μικροροϊκών Κυκλωμάτων ”, GR20130100091, 31 Ιανουαρίου 2013 (“Integrated System for electronic detection of biological components with  Visual Control, based on Microfluidics (Lab-on-Chip)”)
  2. Ελληνική αίτηση διπλώματος ευρεσιτεχνίας : Ι. Ράμφος, Σ. Μπλιώνας, “Παραμετροποιήσιμο βαθμονομούμενο κύκλωμα για παράλληλες μετρήσεις συστοιχίας ηλεκτροχημικών αισθητήρων υπό διαρκή πόλωση σε πραγματικό χρόνο” , GR20120100269, 22 Μαίου 2012, (“Parameterisable, autocallibrated circuit for parallel measurements of electrochemical sensors under continuous bias”)
  3. Ελληνική αίτηση διπλώματος ευρεσιτεχνίας : Α. Δεμίρης, Σ. Μπλιώνας, “Ολοκληρωμένο Σύστημα Οπτικού Ελέγχου, Ποσοτικής και Ποιοτικής Μέτρησης Ροής σε Μικροροϊκά Κυκλώματα”, GR20110100390/2011-02211, 5 Ιουλίου 2011 (“Integrated System for the Visual Control, Quantitative and Qualitative Flow Measurement in Microfluidics”)
  4. Ευρωπαϊκή αίτηση διπλώματος ευρεσιτεχνίας : S. Blionas, “Viterbi Equaliser for Maximum Likelihood Estimation”, EP0671836A2, European Patent Office, 1995.
  5. Ελληνική αίτηση διπλώματος ευρεσιτεχνίας : Σ. Μπλιώνας, "Ολοκληρωμένο Κύκλωμα Προσδιορισμού Μεγιστοπίθανης Ακολουθίας Λαμβανομένων Ψηφιακών Σημάτων", GR 94010109, Οργανισμός Βιομηχανικής Ιδιοκτησίας 1994.