PUBLICATIONS

BOOKS

1. “System Level Design for Reconfigurable Systems-on-Chip”, N. S. Voros, K. Masselos (Editors), Springer, ISBN-10 0-387-26103-6, ISBN-10 0-387-26104-4 (e-book), 2005.

BOOK CHAPTERS

[BC7] K. Masselos, N. S. Voros, “Protoyping of a Hiperlan/2 Reconfigurable System-on-Chip”, in “System Level Design for Reconfigurable Systems-on-Chip”, edited by N. S. Voros, K. Masselos, Springer, ISBN-10 0-387-26103-6, 2005.

[BC6] K. Masselos, N. S. Voros, “Design Flow for Reconfigurable Systems-on-Chip”, in “System Level Design for Reconfigurable Systems-on-Chip”, edited by N. S. Voros, K. Masselos, Springer, ISBN-10 0-387-26103-6, 2005.

[BC5] K. Masselos, N. S. Voros, “Reconfigurable Hardware Technologies”, in “System Level Design for Reconfigurable Systems-on-Chip”, edited by N. S. Voros, K. Masselos, Springer, .

[BC3] K. Masselos, N. S. Voros, “Introduction to Reconfigurable Hardware”, in “System Level Design for Reconfigurable Systems-on-Chip”, edited by N. S. Voros, K. Masselos, Springer, ISBN-10 0-387-26103-6, 2005.

[BC2] K. Tiensyrjä, M. Cupak, K. Masselos, M. Pettissalo, K. Potamianos, Y. Qu, L. Rynders, G. Vanmeerbeeck, N. Voros and Y. Zhang, “SystemC and Ocapi-Xl based System-Level Design for Reconfigurable Systems-on-Chip” in "Advances in Design and Specification Languages for SoCs - Selected contributions from FDL'04" edited by P. Boulet, Springer, ISBN 0-387-26149-4, 2005.

[BC1] K. Masselos, C. E. Goutis, “Power Efficient Synthesis of Sum-of-Products Computations", in “Unified low-power design flow for data-dominated multi-media and telecom applications”, edited by F. Catthoor, Kluwer Academic Publishers, ISBN 0-7923-7947-0, 2000.

JOURNAL ARTICLES

[J29] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation”, The Computer Journal, Oxford Journals, Oxford University Press on behalf of The British Computer Society, doi:10.1093/comjnl/bxp020

[J28] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Data Reuse Exploration under an on-chip Memory Constraint for Low Power FPGA-based Systems”, IET Computers and Digital Techniques, vol 3, No 3, pp. 235-246, May 2009.

[J27] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Combining Data Reuse With Data-Level Parallelization for FPGA Targeted Hardware Compilation: a Geometric Programming Framework”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28, No. 3, pp. 305-315, March 2009 (pdf)

[J26] K. Turkington, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Outer Loop Pipelining in FPGAs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, special issue on Application Specific Processors, Vol. 16, No. 10, pp. 1268-1280, October 2008 (pdf)

[J25] M. Angelopoulou, K. Masselos, P. Cheung, Y. Andreopoulos, “Implementation and Comparison of the 5/3 Lifting 2-D Discrete Wavelet Transform Computation Schedules on FPGAs”, Journal of VLSI Signal Processing Systems, Springer, Special Issue on FPT'06, vol. 51, Issue 1, pp. 3 – 21, April 2008.

[J24] K. Masselos, N. Voros, “Implementation of Wireless Communications Systems on FPGA based platforms”, EURASIP Journal on Embedded Systems, vol. 2007, Issue 1, pp. 1 – 9, January 2007.

[J23] K. Masselos, Y. Andreopoulos, T. Stouraitis, “Performance Comparison of Two-dimensional Discrete Wavelet Transform Computation Schedules on a VLIW Digital Signal Processor”, IEE proceedings on Vision, Image and Signal Processing, vol. 153, No. 2, pp. 173 – 180, April 2006.

[J22] N. S. Voros, C. F. Snook, S. Hallerstede, K. Masselos, “Embedded system design using formal model refinement: An approach based on the combined use of UML and the B language”, Journal on Design Automation for Embedded Systems, Kluwer Academic Publishers, vol. 9, No. 2, pp. 67-99, June 2004.

[J21] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, “Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors”, Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Kluwer Academic Publishers, vol. 37, pp. 53-73, May 2004.

[J20] K. Masselos, A. Pelkonen, M. Cupak, S. Blionas, “Realization of Wireless Multimedia Communication Systems on Reconfigurable Platforms”, Invited Paper, Journal of Systems Architecture, Special Issue on Reconfigurable Systems, Elsevier Publishers, vol. 49, issues 4-6, pp.155-175, September 2003.

[J19] K. Masselos, P. Merakos, S. Theoharis, T. Stouraitis, C. E. Goutis, "Power Efficient Data Path Synthesis of Sum-of-Products Computations", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 3, pp. 446-450, June 2003.

[J18] S. Blionas, K. Masselos, C. Dre, C. Drosos, F. Ieromnimon, D. Metafas, T. Pagonis, A. Pneymatikakis, A. Tatsaki, T. Trimis, A. Vontzalidis, “Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip”, IEICE Transactions on Information Systems, special issue on “Reconfigurable Computing”, vol. E86-D, No.5, pp.901-909, May 2003.

[J17] Y. Andreopoulos, P. Schelkens, G. Lafruit, K. Masselos, J. Cornelis, “High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations”, Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Kluwer Academic Publishers, Special Issue on SiPS'01, vol. 34, pp. 209–226, 2003.

[J16] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, “Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications”, Journal on Design Automation for Embedded Systems, Kluwer Academic Publishers, vol. 8, No. 1, pp. 51-86, March 2003.

[J15] P. Merakos, K. Masselos, S. Theoharis, T. Stouraitis, C. E. Goutis, “Optimization Techniques for Reducing Global Bus Switching Activity in Realizations of Sum-of-Products Computations in DSP Systems”, IEE Proceedings on Circuits Systems and Devices, Vol. 150, No. 1, pp. 16-26, February 2003.

[J14] K. Masselos, S. Theoharis, P. Merakos, T. Stouraitis, C. E. Goutis, "Memory Accesses Reordering for Interconnect Power Reduction in Sum-of-Products Computations", IEEE Transactions on Signal Processing, Vol. 50, No. 11, pp. 2889-2899, November 2002.

[J13] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, “A Systematic Methodology for the Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in Realizations of Multimedia Algorithms on Programmable Processors”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 10, No. 4, pp. 515-518, August 2002.

[J12] N. D. Zervas, K. Masselos, Y. A. Karayiannis and C.E Goutis, "Energy Minimization under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores", VLSI Design Journal, Taylor and Francis Group, Vol. 14, No. 3, pp. 273-286, 2002.

[J11] P. K. Merakos, K. Masselos and C. E. Goutis Power "Power Efficient Hierarchical Scheduling for DSP Transformations", VLSI Design Journal, Taylor and Francis Group, Vol. 14, No. 2, pp. 203-217, 2002.

[J10] K. Masselos, K. Danckaert, F. Catthoor, N. Zervas, C. E. Goutis, H. DeMan, ^“A Specification Refinement Methodology for Power Efficient Partitioning of Data-dominated Algorithms within Performance Constraints", Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Kluwer Academic Publishers, vol. 26, No. 3, pp. 291-317, November 2000.

[J9] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, "Computation Reordering: A Novel Transformation for Low Power DSP Synthesis", VLSI Design Journal, Overseas Publishers Association N. V. / Gordon and Breach Science Publishers, Vol. 10, No. 2, pp. 177-202, 2000.

[J8] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, "Low Power Architectures for Digital Signal Processing", Journal of Systems Architecture, Elsevier Publishers B. V, Vol. 46, Issue 7, pp. 551-571, March 2000.

[J7] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, "Novel Techniques for Bus Power Consumption Reduction in Realizations of Sum-of-Product Computation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 4, pp. 492-497, December 1999.

[J6] K. Danckaert, K. Masselos, F. Catthoor, H. DeMan, C. E. Goutis, "Strategy for Power Efficient Design of Parallel Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 2, pp. 258-265, June 1999.

[J5] K. Danckaert, K. Masselos, F. Catthoor, H. DeMan, “Strategy for Power Efficient Combined Task and Data Parallelism Exploration Illustrated on a QSDPCM Video Codec”, Journal of Systems Architecture, Special issue on Parallel Image Processing, Elsevier Publishers B. V., Vol. 45, Issue 10, pp. 791-808, April 1999.

[J4] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, “Novel Vector Quantization Based Algorithms for Low Power Image Coding and Decoding”, IEEE Transactions on Circuits and Systems II, Vol. 46, No. 2, pp. 193-198, February 1999.

[J3] K. Masselos, T. Stouraitis, C. E. Goutis, "Novel Scheme for Low-Power Classified Vector Quantization Image Coding", IEE proceedings on Vision, Image and Signal Processing, Vol. 145, No. 6, pp. 408-414, December 1998.

[J2] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, “A Novel Algorithm for Low Power Image and Video Coding”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 8, No. 3, pp. 258-263, June 1998.

[J1] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, “Trade-Off Analysis of a Low-Power Image Coding Algorithm”, Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Special Issue on Systematic Trade-Off Analysis in Signal Processing Systems Design, Kluwer Academic Publishers, Vol. 18, No. 1, pp. 65-80, January 1998.

CONFERENCE AND WORKSHOP PUBLICATIONS

[C55] N. Kavvadias, K. Masselos, “Efficient hardware looping units for FPGAs”, IEEE Computer Society Annual Symposium on VLSI, (Kefalonia, Greece), July 2010, pp. 35-40 (pdf)

[C54] T. Lioris, G. Dimitroulakos, K. Masselos, “XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation”, IEEE Computer Society Annual Symposium on VLSI, (Kefalonia, Greece), July 2010, pp. 375-380 (pdf)

[C53] G. Kalogeridou, N. Voros, K. Masselos, “System Level Design of Complex Hardware Applications using ImpulseC”, IEEE Computer Society Annual Symposium on VLSI, (Kefalonia, Greece), July 2010, pp. .473-474

[C52] K. Turkington, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Co-optimization of Datapath and Memory in Outer Loop Pipelining”, IEEE International Conference on Field Programmable Technology, (Taipei, Taiwan), December 2008, pp. 1-8 (pdf)

[C51] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung,, “Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation”, British Computer Society Conference on Visions of Computer Science, (London, UK), September 2008.

[C50] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework”, International Conference on Field Programmable Logic and Applications, (Heidelberg, Germany), September 2008, pp. 179-184.

[C49] K. Turkington, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Pipeline Exploration for Reconfigurable Targets”, Workshop on Application Specific Processors (in conjunction with the Embedded Systems Week), (Salzburg, Austria), October 2007.

[C48] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung,, “Data Reuse Exploration under Area Constraints for Low Power Reconfigurable Systems”, Workshop on Application Specific Processors (in conjunction with the Embedded Systems Week), (Salzburg, Austria), October 2007.

[C47] N. Voros, K. Masselos, “Prototyping of a WLAN System using C++ based Architecture Exploration”, ACM International Mobile Multimedia Communications Conference, (Nafpaktos, Greece), August 2007.

[C46] Q. Liu, G. Constantinides, K. Masselos, P. Y. K. Cheung, “Automatic On-chip Memory Minimization for Data Reuse”, IEEE Symposium on Field Programmable Custom Computing Machines, (Napa Valley, USA), April 2007, pp. 251-260.

[C45] M. Angelopoulou, K. Masselos, P. Cheung, Y. Andreopoulos, “A Comparison of 2-D Discrete Wavelet Transform Computation Schedules on FPGAs”, IEEE International Conference on Field Programmable Technology, (Bangkok, Thailand), December 2006, pp. 181-188.

[C44] K. Turkington, K. Masselos, G. Constantinides, P. Leong, “FPGA Acceleration of the LINPACK Benchmark Using Handel-C and the Celoxica Floating Point Library”, MAPLD International Conference, (Washington, USA), September 2006.

[C43] Q. Liu, K. Masselos, G. Constantinides, “Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm”, International Conference on Field Programmable Logic and Applications, (Madrid, Spain), August 2006, pp. 389-394.

[C42] K. Turkington, K. Masselos, G. Constantinides, P. Leong, “FPGA based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach”, t-size:11.0pt'>

[C41] K. Masselos, N. Voros, Y. Qu, K. Tiensyrjä, M. Cupak, L. Rijnders, M. Pettissalo, “System Level Architecture Exploration for Reconfigurable Systems on Chip”, International Conference on Field Programmable Logic and Applications, (Madrid, Spain), August 2006, pp. 59-64.

[C40] K. Masselos, Y. Andreopoulos, T. Stouraitis, “Execution Time Comparison of Lifting-based 2-D Wavelet Transform Implementations on a VLIW DSP”, IEEE International Symposium Circuits and Systems, (Kos, Greece), May 2006, pp. 923-926.

[C39] K. Masselos, S. Blionas, J-Y. Mignolet, A. Foster, D. Soudris, S. Nikolaidis, “Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform”, International Workshop on Power and Timing Modeling, Optimization and Simulation, (Santorini, Greece), September 2004, pp. 613-622.

[C38] Y. Qu, K. Tiensyrjä, K. Masselos, “System-Level Modeling of Dynamically Reconfigurable Co-Processors”, International Conference on Field Programmable Logic and Applications, (Antwerp, Belgium), August-September 2004, pp. 881-885.

[C37] K. Tiensyrjä, M. Cupak, K. Masselos, M. Pettissalo, K. Potamianos, Y. Qu, L. Rynders, G. Vanmeerbeeck, Y. Zhang, “SystemC and OCAPI-XL Based System-Level Design for Reconfigurable Systems-on-Chip”, Forum on Specification and Design Languages 2004, (Lille, France), September 2004, pp. 428-429.

[C36] K. Masselos, D. Soudris, S. Blionas, "A Reconfigurable System-on-Chip Platform for Wireless Communications" Workshop on Wireless Circuits and Systems, (Vancouver, Canada), May 2004 pp. 20-21.

[C35] E. Theochari, K. Tatas, D. J. Soudris, K. Masselos, K. Potamianos, S. Blionas and A. Thanailakis, “A Reusable IP FFT Core for DSP Applications”, IEEE International Symposium Circuits and Systems, (Vancouver, Canada), May 2004, pp. III.621- III.624.

[C34] K. Tatas, K. Siozios, D. Soudris, K. Masselos, K. Potamianos, S. Blionas, and A. Thanailakis, “Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms” International Workshop on Power and Timing Modeling, Optimization and Simulation, (Torino, Italy), September 2003, pp. 430-439.

[C33] A. Pelkonen, K. Masselos, M. Cupak, “System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC”, Proceedings of International Symposium on Parallel and Distributed Processing (Reconfigurable Architectures Workshop), ISBN: 0-7695-1926-1, April 2003, pp. 174-181.

[C32] G. Koutroumpezis, K. Tatas, D. Soudris, S. Blionas, K. Masselos, and A. Thanailakis “Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-grain Implementations”, International Conference on Field Programmable Logic and Applications, (Montpellier, France), September 2002, pp. 1027-1036.

[C31] S. Blionas, K. Masselos, C. Dre, C. Drosos, F. Ieromnimon, T. Pagonis, A. Pneymatikakis, A. Tatsaki, T.Trimis, A. Vontzalidis and D. Metafas “A HIPERLAN/2 – IEEE 802.11a Reconfigurable System-on-Chip”, International Conference on Field Programmable Logic and Applications, (Montpellier, France), September 2002, pp. 1080-1083.

[C30] K. Masselos, P. Merakos, C. E. Goutis, “Power Efficient Vector Quantization Design Using Pixel Truncation”, International Workshop on Power, Timing, Modeling, Optimization and Simulation, (Seville, Spain), September 2002, pp. 409-418.

[C29] Y. Andreopoulos, K. Masselos, P. Schelkens, G. Lafruit, J. Cornelis “Cache-Misses and Energy-Dissipation Results for JPEG-2000 Filtering”, International Conference on Digital Signal Processing, special session JPEG-2000 Implementations: Algorithms and Architectures, (Santorini, Greece), July 2002, pp. 201-210.

[C28] D. Soudris, K. Masselos, S. Blionas, S. Siskos, S. Nikolaidis and K. Tatas “AMDREL: Designing Embedded Reconfigurable Hardware Structures for Future Reconfigurable Systems-on-Chip for Wireless Communication Applications”, IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip, Chances, Application, Trends, (Hamburg, Germany), April 2002.

[C27] S. Blionas, K. Masselos, C. Dre, F. Ieromnimon, T. Pagonis, A. Pneymatikakis, A. Tatsaki, T.Trimis, A. Vontzalidis and D. Metafas, “Design Story: A Hiperlan2/IEEE802.11x Reconfigurable SoC for indoor WLANs and outdoor wireless links. A pilot project for the future generation configurable wireless communications products”, IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip, Chances, Application, Trends, (Hamburg, Germany), April 2002.

[C26] K. Masselos, S. Blionas, “Reconfigurability requirements of wireless communication systems”, IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip, Chances, Application, Trends, (Hamburg, Germany), April 2002.

[C25] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, “Effect of Data Transfer and Storage Optimization on Design Quality Factors of Multimedia Algorithms Realized on Instruction Set Processors”, International Workshop on Power, Timing, Modeling, Optimization and Simulation, (Yverdon-les-bains, Switzerland), September 2001, pp. 3.3.1-3.3.10.

[C24] K. Masselos, F. Catthoor, A. Kakarudas, C. E. Goutis, H. DeMan, “Memory Hierarchy Layer Assignment for Data Re-Use Exploitation in Multimedia Algorithms Realized on Predefined Processor Architectures”, IEEE International Conference on Electronics Circuits and Systems, (Malta), September 2001, pp. I.285-I.288.

[C23] K. Masselos, Y. A. Karayiannis, I. Andreopoulos, T. Stouraitis "Development of a Power Efficient Image Coding Algorithm Based on Integer Wavelet Transform", IEEE International Conference on Electronics Circuits and Systems, (Beirut, Lebanon), December 2000, pp. 457-460.

[C22] K. Masselos, S. Theoharis, P. Merakos, T. Stouraitis, C. E. Goutis "Low Power Synthesis of Sum-Of-Products Computation", ACM/IEEE International Symposium Low-Power Electronics and Design (Rapallo/Portacino Coast, Italy), July 2000, pp. 234-237.

[C21] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, "A Performance-Oriented Use Methodology of Power Optimizing Code Transformations for Multimedia Applications Realized on Programmable Multimedia Processors", IEEE Workshop on Signal Processing Systems, (Taiwan), November 1999, pp. 261-270.

[C20] N. D. Zervas, K. Masselos, C. E. Goutis, "Data-Reuse Exploration for Low-Power Realization of Multimedia Applications on Embedded Cores", International Workshop on Power, Timing, Modeling, Optimization and Simulation, (Kos, Greece), October 1999, pp. 71-80.

[C19] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, " Code Size Effects of Power Optimizing Code Transformations for Embedded Multimedia Applications", International Workshop on Power, Timing, Modeling, Optimization and Simulation, (Kos, Greece), October 1999, pp. 61-70.

[C18] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, “System-Level Power Optimizing Data-Flow Transformations For Multimedia Applications Realized on Programmable Multimedia Processors”, IEEE International Conference Electronics Circuits and Systems, (Pafos, Cyprus), September 1999, pp. III.1733-III.1736.

[C17] K. Masselos, K. Danckaert, F. Catthoor, C. E. Goutis, H. DeMan, " A Methodology for Power Efficient Partitioning of Data-dominated Algorithm Specifications within Performance Constraints", IEEE International Symposium Low-Power Electronics and Design, (San Diego, USA), August 1999, pp. 270-272.

[C16] N. D. Zervas, K. Masselos, O. Koufopavlou, C. E. Goutis, "Power Exploration of Multimedia Applications realized on Embedded Cores", IEEE International Symposium Circuits and Systems, (Orlando, USA), May-June 1999, pp. IV.378-IV.381.

[C15] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, "Low Power Synthesis of Sum-Of-Product Computation in DSP Algorithms", IEEE International Symposium Circuits and Systems, (Orlando, USA), May-June 1999, pp. VI.420-VI.423.

[C14] K. Masselos, F. Catthoor, C. E. Goutis, H. DeMan, "Interaction between Sub-word Parallelism Exploitation and Low Power Code Transformations for VLIW Multi-media Processors", IEEE Alessandro Volta Memorial International Workshop on Low Power Design, (Como, Italy), March 1999, pp.52-60.

[C13] K. Masselos. P. Merakos, T. Stouraitis, C. E. Goutis, “Low Power Implementation of Discrete Wavelet Transform”, IX European Signal Processing Conference, (Rodos, Greece), September 1998, pp. II.869-II.872.

[C12] N. D. Zervas, K. Masselos, C. E. Goutis, "Code Transformations for Embedded Multimedia Applications: Impact on Power and Performance", Power Driven Microarchitecture Workshop of the International Symposium Computer Architecture, (Barcelona, Spain), June 1998, pp. 20-24.

[C11] K. Masselos. P. Merakos, T. Stouraitis, C. E. Goutis, “A Novel Methodology for Power Consumption Reduction in a Class of DSP Algorithms”, IEEE International Symposium Circuits and Systems, (Monterey, USA), June 1998, pp. VI.199-VI.202.

[C10] K. Masselos, T. Stouraitis, C. E. Goutis, “Novel Codebook Generation Algorithms for Vector Quantization Image Compression”, IEEE International Conference Acoustics Speech and Signal Processing, (Seattle, USA), May 1998, pp. V.2661-V.2664.

[C9] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, “Low-Power Image Coding using a Block Transformation”, IEEE International Conference Electronics Circuits and Systems, (Cairo, Egypt), December 1997, III.1067-III.1071.

[C8] K. Masselos, G. Kittes, Y. A. Karayiannis, and T. Stouraitis, “Image Coding using Vector Quantization and a Logarithmic-Search Fractal Coding Scheme”, IEEE International Conference Electronics Circuits and Systems, (Cairo, Egypt), December 1997, pp. III.1072-III.1076.

[C7] P. K. Merakos, K. Masselos, O. Koufopavlou, S. Nikolaidis and C. E. Goutis, “A Novel Transformation for Reduction of Switching Activity in FIR Filters Implementation”, IEEE International Conference Digital Signal Processing, (Santorini, Greece), July 1997, pp. II.653-II.656.

[C6] K. Masselos, G. Kittes, Y. A. Karayiannis, and T. Stouraitis, “Image Coding using a Fractal/Vector Quantization Model”, IEEE International Conference Digital Signal Processing, (Santorini, Greece), July 1997, pp. II.797-II.800.

[C5] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, “Novel Codebook Design Techniques for Vector Quantization Image Compression”, IEEE International Symposium Circuits and Systems, (Hong Kong), June 1997, pp. II.1321-II.1324.

[C4] K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, “Low-Power Image Decoding using Fractals”, IEEE International Conference Electronics Circuits and Systems, (Rodos, Greece), October 1996, pp. II.748-II.751.

[C3] K. Masselos, A. Alexopoulou, “Design of a Position Sensitive Integrated Multidetector”, IEEE International Conference Electronics Circuits and Systems, (Rodos, Greece), October 1996, pp. II.923-II.926.

[C2] K. Masselos, K. Karagianni, Y. A. Karayiannis, T. Stouraitis, “A Parallel Image Compression Scheme based on Fractal Coding and Vector Quantization”, IEEE International Conference Electronics Circuits and Systems, (Rodos, Greece), October 1996, pp. II.712-II.715.

[C1] Y. A. Karayiannis, K. Masselos, T. Stouraitis, “Image Compression using Fractal Coding and Vector Quantization”, IEEE International Workshop Non-Linear Signal and Image Processing, (Halkidiki, Greece), June 1995, pp. I.210-I.213.